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Preliminary Data Sheet
AS8520
LIN Tr a ns ce i ve r w it h Vol t ag e Re gu la t or, A t t e nua t or, Relay Drivers, MCU Interface for Automotive Applications
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1 General Description
The AS8520 is a companion IC for sensor and actuator LIN slaves. The device provides application specific add-ons, such as the resistive attenuator for battery voltage sensing, a micro controller interface to control 2 relay drivers, to access control register, and diagnosis options. The AS8520 has a window watchdog which can be enabled as a factory option.
Micro controller 4-wire interface for relay driver control, device configuration, status and diagnosis read out, register read / write Operating modes: Normal and Standby or Normal and Sleep as a factory option Window Watchdog with timing options if factory enabled Backup registers to store MCU data during VCC shut down Voltage attenuator with disable. Factory selectable ratio options of 21 and 481 Two low side relay drivers RON < 5 -40C to +125C ambient operating temperature AEC Q 100 automotive qualified 6kV ESD on LIN pin according to IEC 61000-4-2 24bit chip ID for traceability and module ID 24-pin QFN (6x6) package
2 Key Features
Operating voltage 6 to 18V, max. 42V for 500 ms Linear, low-drop voltage regulator: VCC = 5V 3% or VCC = 3.3V as a factory option 50mA load current Typical 35 A quiescent current in standby mode Undervoltage detection with reset output, factory adjustable undervoltage threshold and reset time LIN bus transceiver with load independent slew control conforming to LIN 2.0 and SAE J2602, short circuit protection, TX time out fail safe feature, over temperature warning and shut down Figure 1. AS8520 Lin Transceiver Block Diagram
3 Applications
The AS8520 is suitable for small actuator or sensor LIN slaves. The device is ideal for LIN 2.0/2.1 network applications like Window lift actuators, Sunroof actuators, Seat actuators and battery sensors.
VSUP PORVSUP
LDO PORVCC RESET_VCC_N Control Signals LIN Wakeup Receiver WWD Output
VCC
Temperature Limiter TSHD
RESET_VSUP_N EN Mode Control RESET_VSUP_N VBAT_DIV VBAT Resistive divider
Reset Block VCC
RESET
VSUP
RX VSS BUS Slew Control LIN Transceiver LDRIVE1 SPI Interface, Diagnostic, Window Watchdog (WWD) GND CS SCLK SDO SDI GND VCC TX 30k Transmitter VCC
LDRIVE2
VSS
Relay driver
AS8520
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Contents
1 General Description.................................................................................................................................................................... 1 2 Key Features ............................................................................................................................................................................... 1 3 Applications ................................................................................................................................................................................ 1 4 Pin Assignments......................................................................................................................................................................... 4
4.1 Pin Descriptions........................................................................................................................................................................................ 4
5 Absolute Maximum Ratings....................................................................................................................................................... 6 6 Electrical Characteristics........................................................................................................................................................... 7
6.1 Detailed System and Block Specifications ............................................................................................................................................... 8 6.1.1 Low Dropout Regulator................................................................................................................................................................. 8 6.1.2 LIN Transceiver ............................................................................................................................................................................ 9 6.1.3 VCC Undervoltage Reset and Window Watchdog...................................................................................................................... 11
7 Detailed Description ................................................................................................................................................................. 14
7.1 Block Description.................................................................................................................................................................................... 14 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Voltage Regulator (LDO) ............................................................................................................................................................ 14 Temperature Limiter ................................................................................................................................................................... 14 VSUP Undervoltage Reset ......................................................................................................................................................... 14 RESET........................................................................................................................................................................................ 14 VCC Undervoltage Reset............................................................................................................................................................ 15 Window Watchdog (WWD) ......................................................................................................................................................... 15 Resistive Divider ......................................................................................................................................................................... 16 HV Low Side Relay Driver Switches........................................................................................................................................... 16 LIN Transceiver .......................................................................................................................................................................... 16 Normal Mode .............................................................................................................................................................................. 16 Standby Mode............................................................................................................................................................................. 17 Sleep Mode................................................................................................................................................................................. 17 Temporary Shutdown Mode ....................................................................................................................................................... 17 Thermal Shutdown State ............................................................................................................................................................ 17
7.2 Operating Modes and States.................................................................................................................................................................. 16
7.3 State Diagram......................................................................................................................................................................................... 19
8 Application Information............................................................................................................................................................ 20
8.1 Initialization............................................................................................................................................................................................. 20 8.2 Wake-Up................................................................................................................................................................................................. 21 8.3 Over-Temperature Shutdown ................................................................................................................................................................. 21 8.4 LIN BUS Transceiver .............................................................................................................................................................................. 21 8.4.1 Transmit Mode............................................................................................................................................................................ 21 8.4.2 Receive Mode............................................................................................................................................................................. 21 8.5 RX and TX Interface ............................................................................................................................................................................... 22 8.5.1 Input TX ...................................................................................................................................................................................... 22 8.5.2 Output RX ................................................................................................................................................................................... 22 8.6 MODE Input EN...................................................................................................................................................................................... 23 8.7 Serial Port Interface................................................................................................................................................................................ 25 8.7.1 Device Configuration using 4-Wire Serial Port ........................................................................................................................... 25 8.8 Control and Diagnosis Registers ............................................................................................................................................................ 29 8.8.1 Definition of Control and Status Registers.................................................................................................................................. 29 8.9 ESD/EMC REMARKS ............................................................................................................................................................................ 31
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8.9.1 General Remarks........................................................................................................................................................................ 31 8.9.2 ESD-Test .................................................................................................................................................................................... 31 8.9.3 EMC........................................................................................................................................................................................... 31
9 Package Drawings and Markings............................................................................................................................................ 32 10 Ordering Information.............................................................................................................................................................. 34
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4 Pin Assignments
Figure 2. Pin Assignments (Top View)
EN 24 VSUP 1 23 22 21 VSS 20 VCC 19 18
RESET
LIN
2
17
TX
VSS
3
AS8520
24 pin QFN-24
16
RX
VBAT_DIV
4
15
CS
VBAT
5
14
SDO
LDRIVE1
6 7 8 9 10 11
13 12 SDI
SCLK
LDRIVE 2
4.1 Pin Descriptions
Table 1. Pin Descriptions Pin Name VSUP LIN VSS VBAT_DIV VBAT LDRIVE1 LDRIVE2 NC NC NC NC SDI SCLK SDO CS RX TX RESET Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Positive Power Supply LIN Bus GND Attenuated battery voltage Battery voltage sensing line Low side driver Low side driver Not connected. Not connected. Not connected. Not connected. Serial data in Serial clock Serial data out Chip select for Serial Interface LIN transceiver receive signal LIN transceiver transmit signal Digital Output referenced to VCC, active low Description
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Table 1. Pin Descriptions Pin Name VCC VSS NC NC NC EN Pin Number 19 20 21 22 23 24 Description Regulated 5V/3.3V supply for loads up to 50mA, OTP selectable (factory programmable) GND Not connected. Not connected. Not connected. High voltage compatible. Enable pin with pull down to VSS, active high.
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5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VSUP EN VCC DC Supply Voltage LIN VBAT LDRIVE1, LDRIVE2 RESET, RX, TX, CS, SCLK, SDO, SDI, VBAT_DIV Input current (latchup immunity) Iscr Min -0.3 Max 18 42 -0.3 -0.3 -27 -27 -0.3 -0.3 -100 2 4 Electrostatic Discharge (ESD) 8 6 0.5 0.1 Total operating power dissipation (all supplies and outputs) Pt Thermal Package Resistance (Rth) Storage temperature (Tstrg) Package body temperature (Tbody) Humidity non-condensing 5 -55 0.75 33 +150 +260 85 W K/W C C % The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC JSTD-020C "Moisture/Reflow Sensitivity Classification for Non hermetic Solid State Surface Mount Devices". kV VSUP + 0.3 7 +40 +42 50 VCC + 0.3 100 Units V V V V V V V mA Norm: Jedec 78 For on board signals VCC, TX, RX, Reset, CS, SCLK, SDO, SDI, VBAT_DIV, EN For VBAT, VSUP, VSS, LDRIVE1, LDRIVE2 LIN to GND, HBM Model LIN to GND, IEC6100-4-2 LIN to GND, CDM LIN to GND, MM QFN 24 in still air, soldered on JEDEC standard board @125 ambient, static operation = no time limit Soldered on JEDEC standard board @125 ambient, static operation = no time limit Comments Transient up to 500ms duration
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6 Electrical Characteristics
Table 3. Electrical Characteristics Symbol Operating Conditions Normal operating condition VSUP VSS TAMB Isupp Positive Supply Voltage Negative Supply Voltage Ambient temperature Supply Current DC/AC Characteristics for Digital Inputs and Outputs Enable Input VIH VIL ILEAK Ipd_en TX, CS Input VIH VIL ILEAK Ipu SDI, SCLK VIH VIL ILEAK Ipd_spi RESET, SDO VOH VOL RX VOH VOL Ipu_reset High level output voltage Low level output voltage Pull-up current VSUP 6V, I = 1 mA VSUP 6V, I = 1 mA Pulled up to VCC -100 VCC-0.5 VSS + 0.4 -30 V V A High level output voltage Low level output voltage VSUP 6V, I = 1 mA VSUP 6V, I = 1 mA VCC-0.5 VSS + 0.4 V V High level input voltage Low level input voltage Input leakage current Pull down current SDI, SCLK pulled to VSS -1 30 0.8VCC 0.2VCC +1 100 V V A A High level input voltage Low level input voltage Input leakage current Pull up current TX = VCC RX, TX,CS pulled to VCC -1 -100 0.8VCC 0.2VCC +1 -30 V V A A High level input voltage Low level input voltage Input leakage current Pull down current EN = L EN = VCC = 5V -1 30 0.8VCC 0.2VCC +1 100 V V A A
1
Parameter
Conditions
Min 6
Typ
Max 18 27 42
Units V V V V C mA
Jump-start/ over-voltage condition Load dump condition 0 Max junction temperature (TJ) 150C -40
+125 65
1. All pull-up, pull-downs are implemented with active devices. RESET, RX, SDO have been measured with 10pF load.
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6.1 Detailed System and Block Specifications
Table 4. System Specifications Symbol Parameter Conditions No load on VCC, LIN inactive, VSUP = 14V, RES_DIV enabled IDDnom Current consumption normal mode No load on VCC, LIN active, VSUP = 14V, RES_DIV enabled No load on VCC, LIN inactive, VSUP = 14V, RES_DIV disabled IDDstby IDDsleep Current consumption standby mode Current consumption sleep mode @ 85C ambient (no load) @125C ambient (no load) @ 85C ambient (no load) @ 125C ambient (no load) Min Typ 300 700 250 40 45 30 35 A A A Max Units
6.1.1
Low Dropout Regulator
The LDO is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (VCC) from the battery supply voltage (VSUP). (6V < VSUP < 18V; -40C < TJ < +150C; all voltages are with respect to ground (VSS); positive current flows into the pin), normal operating mode if not otherwise mentioned. Table 5. LDO Block Specifications Symbol VSUP Parameter Battery Voltage Range Conditions Default, Need safe operating area calculations with package Rth Load < 50mA Factory option, load < 50mA 50 to 65mA VCC Output Voltage Range Factory option, 50 to 65mA Standby mode @ ICC < 5mA Load-dump condition, Iload < 50mA Factory option, Standby mode @ ICC < 5mA ICC_SH dVCC1 LOREG_SM LOREG_NM CL1 ESR1 CL2 ESR2 CSUP1E ESR1_CSUP CSUP2C ESR2_CSUP Output Short Circuit Current Line Regulation Load Regulation (Standby mode) Load Regulation (Normal mode) Output Capacitor (Electrolytic) Output Capacitor (Ceramic) Input capacitor (Electrolytic) Input capacitor (Ceramic) For EMC suppression For EMC suppression Normal mode Standby mode VCC / VSUP VCC / ICCn (for Iload > 500uA) VCC / ICCn (for Iload > 500uA) 2.2 1 100 0.02 10 1 100 0.02 3 50 5 Min 6 4.85 3.15 4.5 2.9 4.5 3.3 Typ 12 5.0 3.3 Max 18 5.15 3.45 5.15 3.45 5.5 5.5 3.6 250 250 8 10 1 10 10 220 1 100 10 220 1 mA mV/V mV/mA mV/mA F nF F nF V Units V
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6.1.2
LIN Transceiver
(4.5V < VCC < 5.5V; 6V < VSUP < 18V; -40C < TJ < 150C, VBUS is the voltage on the LIN node. All voltages are with respect to ground (VSS); positive current flows into the pin. Table 6. DC Electrical Characteristics Symbol Driver Ibus_lim LIN_VOL Pull-up resistor Ibus_leak_rec Receiver Ibus_leak_dom Ibus_no_GND Ibus_no_bat Vbus_dom Vbus_rec Vbus_cnt Vhys Vbus_cnt = (Vth_dom + Vth_rec)/2 Vhys = (Vth_dom - Vth_rec)
1 1
Parameter
Conditions Current limitation in Dominant State LIN = VSUP_max Output Voltage BUS (dominant state), ILIN = 40mA (short-circuit condition tested at VOL = 2.5V) Normal mode (recessive BUS level on TX pin) Driver OFF; VSUP = 7.3V, 8VMin
Typ
Max
Units
40
120
200 2
mA V k A
20
40
60 20
Input Leakage current at receiver
Driver OFF; Vbus = 0v; VSUP = 12v; VCC = 5V VSS = VSUP; VSUP = 12V; 0V-1 -1 1 100 0.4 0.6 0.475 0.05 0.525 0.175
mA mA A VSUP VSUP VSUP VSUP
1. Vth_dom: Receiver threshold of the recessive to dominant LIN bus edge Vth_rec: Receiver threshold of the dominant to recessive LIN bus edge Table 7. AC Electrical Characteristics Symbol D1 (worst case 20Kbps transmission) D2 (worst case 20kbps transmission) D3 (worst case 10.4kbps transmission) Parameter Conditions Vth_rec(max) = 0.744 x VSUP; Vth_dom(max) = 0.581 x VSUP; VSUP = 6.0V...18V; tbit = 50s; D1 = tbus_rec(min) / (2 x tbit) OTP selection = High Slew Mode Vth_rec (min) = 0.422 x VSUP; Vth_dom (min) = 0.284 x VSUP; VSUP = 6V...18V; tbit = 50s; D2 = tbus_rec(max) / (2 x tbit) OTP selection = High Slew Mode Vth_rec (max) = 0.778 x VSUP; Vth_dom (max) = 0.616 x VSUP; VSUP = 6.0V...18V; tbit = 96s; D3 = tbus_rec(min) / (2 x tbit) OTP selection = Low Slew Mode Min Typ Max Units
0.369
0.581
0.417
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Table 7. AC Electrical Characteristics Symbol D4 (worst case 10.4kbps transmission) tdLR tdHR tRS twake tsln tnsl trec_deb Cint Table 8. Temperature Limiter Symbol Tsd Tret Totset Totclear Parameter Shut down temperature Return temperature Over-temp warning flag set Over-temp warning flag clear Conditions junction temperature
12
Parameter
Conditions Vth_rec (min) = 0.389 x VSUP; Vth_dom (min) = 0.251 x VSUP; VSUP = 6V...18V; tbit = 96s; D4 = tbus_rec(max) / (2 x tbit) OTP selection = Low Slew Mode VCC = 5v; Propagation delay bus dominant to RX LOW VCC = 5v; Propagation delay bus dominant to RX HIGH Receiver Delay symmetry Wake-up delay time Transition from standby mode to normal mode (clock frequency is 128KHz 25%) Transition from normal mode to standby mode (clock frequency is 128KHz 25%) Receiver De-bounce time Internal capacitance of the LIN node configured as a slave
Min
Typ
Max
Units
0.59
6 6 -2 30 4 6 0.6 1 250 2 150
s s s s Clock cycles Clock cycles s pF
Min 144 126 126 108
Typ
Max 176 154 154 132
Units C C C C
The temperature beyond which the warning flag is set. The return temperature when the warning flag is cleared
1. During shut down, the sensor must be powered by VSUP. 2. Thermal shut down disables LDO and sets all drivers to high impedance, the IC returns from shut down with POR Table 9. TX Timeout Watchdog Symbol tlin_wdog Parameter Time out duration (dominant state) Conditions Min 0.5 Typ 1 Max 2 Units s
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Figure 3. LIN Timing Diagram
tbit TXD
tbit
tbus_dom(max) LIN
Vth_rec(max) Vth_dom(max) Vth_rec(min) Vth_dom(min)
tbus_rec(min)
tbus_dom(min)
6.1.3
tbus_rec(max)
VCC Undervoltage Reset and Window Watchdog The values in this table are valid for normal and standby modes. All parameters are tested unless mentioned. Table 10. Electrical Characteristics Symbol Vuvr_off Vuvr_on Vuvr1_off Vuvr1_on Vuvr2_off Vuvr2_on Vuvr3_off Vuvr3_on Vhyst_vcc trr Vsuvr_off Vsuvr_on Parameter VCC under-voltage threshold off VCC under voltage threshold on VCC under voltage threshold off (Default) VCC under voltage threshold on (Factory Option) VCC under voltage threshold off (Factory Option) VCC under voltage threshold on (Factory Option) VCC under-voltage threshold off (Factory Option) VCC under voltage threshold on (Factory Option) Hysteresis of under-voltage threshold on/off VCC Spike filter on VCC VSUP under-voltage threshold off VSUP under-voltage threshold on Hysteresis on under-voltage threshold on/off VSUP WD_TCL WD_TSV WWD non-service time (if factory enabled) WWD Service - time (if factory enabled) RESET will be generated
1
Conditions Rising edge of VCC Falling edge of VCC Rising edge of VCC Falling edge of VCC Rising edge of VCC Falling edge of VCC Rising edge of VCC Falling edge of VCC Default and all other OTP options To remove disturbance BOR level (considered to be the Master Reset for AS8520)
Min 2.55 2.3 3.0 2.75 3.5 3.25 4.0 3.75 0.1 4
Typ
Max 2.95 2.7 3.4 3.15 3.9 3.65 4.4 4.15
Units V V V V V V V V V s
0.25
0.4
3.85 3.25 0.2 0-75 75-150 0.5 0 -100 0.7 0-125
V V V ms ms
RESET will not be generated
100-200 125-250
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Table 10. Electrical Characteristics (Continued) Symbol tRes Tshd Parameter Reset delay time Temporary shutdown reset active time Conditions 4ms, 16ms, 32ms (typ) are factory options (min = -25% and max = +50% of typical) Min 6 0.1 Typ 8 Max 12 1 Units ms s
1. -40%, -20%, +20%, +60%, and +100% timings are available as factory options. Table 11. Resistive Divider Symbol RRHRL Vin_bat Vbat_leak TCRHRL Temperature drift of dividing ratio Parameter Division ratio
1
Conditions
Min 20.8
Typ 21
Max 21.2 18 1 2
Units
Input Battery Voltage Range
LDO must turn ON VBAT = 18V from -40 to +125 deg (guaranteed by design) 11V6.8 -1
V A %
1. A division ratio of 481 is available as factory option. Table 12. Low Side Relay Driver Symbol VOL Vovthh Vovthl Vovhys Vcl Lload Rload Ron Ioz Table 13. SPI Interface Symbol General BRSPI TSCLKH TSCLKL Write Timing tDIS tDIH TCSH Read Timing tDOD tDOHZ Data out delay Data out to high impedance delay Time for the SPI to release the SDO bus 80 80 ns ns Data in setup time Data in hold time CS hold time 20 10 20 ns ns ns Bit rate Clock high time Clock low time 2 2 250 Kbps s s Parameter Conditions Min Typ Max Units Parameter Output low level Battery Over Voltage Threshold HIGH Battery Over Voltage Threshold LOW Battery Over Voltage Hysteresis Drain to Source clamp Voltage Load Inductance Load Resistance ON Resistance Leakage in off state Vcl < 50V, Iload = 10mA Conditions @ 80 mA Drivers will turn off when exceeded 20 18 1 VSUP + 1 0.125 80 Min Typ Max 0.4 24 22 3 VSUP + 5 0.25 120 5 1 Units V V V V V H A
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Table 13. SPI Interface Symbol Parameter Clock setup time (CLK polarity) Clock hold time (CLK polarity) Conditions Setup time of SCLK with respect to CS falling edge Hold time of SCLK with respect to CS falling edge Min Typ Max Units Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity) tCPS tCPHD 20 20 ns ns
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7 Detailed Description
The AS8520 chip consists of a low drop-out regulator 5V/50mA, two low-side relay drivers, a resistive divider to monitor battery voltage and a LIN bus transceiver, which is a bi-directional bus interface for data transfer between LIN bus and the LIN protocol controller. Additionally integrated is a RESET unit with a power-on-reset delay and a programmable watchdog time. It also includes a watchdog time-out on LIN TX node to indicate if the microcontroller is stuck in a loop and the LIN bus remains in dominant time for more than the necessary time.
7.1 Block Description
The main blocks of the AS8520 are explained below.
7.1.1
Voltage Regulator (LDO)
The voltage regulator has three operating modes. The features of the operating modes are given below: Normal mode: Stability to be better 0.15V over input range and temperature for load current up to 50mA. The LDO Output provides a voltage of 5V (3.3V as OTP option). Standby mode: The Standby mode is a low quiescent current mode used in car applications that are always switched on. The load current in standby mode is 5mA. Quiescent current (no load) is less than 25A typically at room temperature. Power down mode: The Power down or temporary shutdown of the regulator can be set by a register bit. This bit can be written through 4wire MCU interface. The LDO takes the input from bandgap and scales it up to the required voltage. The LDO starts charging only after the POR-VSUP event occurs (RESET_VSUP_N switched from low to high). The LDO can be powered-down by a control signal (temporary shutdown register) for the temporary shutdown mode.
7.1.2
Temperature Limiter
Temperature limiter produces a power down when temperature exceeds 160C 10%. It powers up and generates a reset when it returns to 140C 10% junction temperature. During thermal shut down, temperature sensor is supplied by VSUP. There is an option control bit provided to enable or disable this temperature monitoring circuit. During the temperature ramp-up phase, as soon as the temperature exceeds 140C 10%, a warning signal is issued and is written into the diagnostic register, which can be read through the SPI interface.
7.1.3
VSUP Undervoltage Reset
VSUP undervoltage reset generates a reset RESET_VSUP_N, switched from low to high when VSUP ramps up above VSUVR_OFF. This is used to enable proper initialization of mode control and diagnostic registers. If VSUP < VSUVR_ON, then RESET_VSUP_N switches from high level to low level (active). This is considered to be the master reset and will have the highest priority over all other signals. As soon as VSUP < VSUVR_ON, the LDO, LIN Transceiver is completely shut off and system comes to a complete stop. AS8520 enters into the normal operating mode only after VSUP > VSUVR_OFF.
7.1.3.1 7.1.3.2
VSUP Undervoltage in Normal Mode VSUP Undervoltage in Standby Mode / Sleep Mode
Supply Voltages below VSUVR_OFF and above VSUVR_ON do not influence the voltage regulator. The output voltage VCC follows VSUP.
No exit from the sleep mode or standby mode take place if the VSUP voltage drops down to VSUVR_OFF. If VSUP goes below VSUVR_ON, RESET_VSUP_N is active and resets the mode control and diagnostic register. The voltage regulator, LIN Transceiver modules are turned off. If VSUP rises again above VSUVR_OFF, RESET_VSUP_N is switched from low to high. The system enters normal mode where LIN Transceiver and LDO are switched on.
7.1.3.3
VSUP Undervoltage in Low Slew Mode
The behavior of AS8520 at low VSUP voltages is equal to the sleep mode. The low slew mode (set by control register through serial interface as an option) will be cancelled, if VSUP drops below VSUVR_ON in this mode. The AS8520 enters the normal mode, if VSUP rises again above VSUVR_OFF.
7.1.4
RESET
Reset generates an external RESET signal to reset the microcontroller and all other external circuits. The reset functionality is illustrated in Figure 4. Reset consists of a digital buffer at the output. RESET signal can be affected by RESET_VCC_N (which is the under-voltage reset on VCC) and Window watchdog output. All those conditions which cause a drop in the VCC voltage will be detected from the low voltage reset unit, which in-turn generates a reset signal. States like Temporary shut-down, Over-temperature monitor will influence the RESET output through RESET_VCC_N signal only.
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Figure 4. Reset Functionality
VSUP
T>Tj VCC VUVR_OF F VUVR_ON
TtRes trr RESET
tRes
tRes MISSING WATCHDOG ACCESS tRes
tRes
Initialisation
Thermal shutdown
Spike VSUP
Low voltage VSUP
Current limitation active
VCC Undervoltage Reset The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of the VCC gives an under-voltage reset "off" and the falling edge of the VCC gives an under-voltage reset "on". This under-voltage signal is used to control the RESET output. When VCC rises up Vuvr_off for a period greater than reset duration (tRes) then RESET_VCC_N switches from low level to high level and pin RESET is inactive (high). If VCC falls below Vuvr_on for a period greater than a predetermined delay (trr) then RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initialize Window watchdog timer, TX time-out, Test control circuits, 4-wire SPI, and logic associated with SPI (everything other than the SPI control registers). VCC under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.
7.1.5
7.1.6
Window Watchdog (WWD)
To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated by external MCU through SPI interface. If the window is missed, a reset on the RESET pin with certain reset time (tRes) is generated. The WWD function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions, microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit is turned on after the RESET pin goes back to high (inactive). If VCC < Vuvr_on, WWD circuit is switched off. When the WWD function is enabled, there is a 3-bit factory programming available to set the trigger window.
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Figure 5. Window Watchdog Trigger
Period
Non-Service time (WD_TCL) 50 % Trigger restart period Trigger via SPI Last trigger point Earliest possible trigger point (System will not RESET) Unwanted trigger point (System will be RESET)
Service time (WD_TSV) 100 %
latest possible trigger point (System wil not be RESET) Valid Trigger point (System will not be RESET)
7.1.7
Resistive Divider
The resistive divider acts as a battery voltage attenuator. The output of this resistive divider can be connected to an ADC for monitoring the battery voltage. The division ratio of resistive divider is 21 but can be set also to 481 as a factory programming option. Both divider options can be disabled in standby mode using the EN signal. Reverse polarity protection of VBAT pin is provided.
7.1.8
HV Low Side Relay Driver Switches
Two NMOS open drain relay driver devices provide over voltage protection. The Driver is disabled if the MCU software hangs up (watchdog reset or time out WD for LIN TX). The input to the drivers is given through SPI (Low-side driver data register). If over voltage occurs, the Relay driver turns off irrespective of the input. The driver stays turned off till the voltage returns back to the normal operating range. An optional control bit available in the Device configuration register, which can be used to switch off the drivers independently to save power. The relay drivers are disabled using the SPI.
7.1.9
LIN Transceiver
The transceiver provides short circuit limitation, hardware watchdog and over temperature shut down features. The TX watchdog timer is active when TX is pulled low (active). As soon as the TX watchdog timeout occurs, the LIN bus is released from dominant state to recessive state. The LIN transceiver has a pull-up resistor (for the slave node; extra resistor externally for the master node) to the VSUP. A diode protection is available to protect it from back supply from bus line. The LIN transmitter has the basic functionality of relaying the data from the micro-controller on to the LIN. The data on the LIN needs to have controlled slew to have reduced EMI. The receiver relays the data from the LIN to the micro-controller. This transmitter has optimized EMC performance across different loading conditions conforming to the LIN 2.1 standards. The wake-up detects a wake up event on the LIN.
7.2 Operating Modes and States
The AS8520 provides four main operating modes "normal", "sleep/stand-by" (programmed by OTP), "temporary shutdown" and "thermal shutdown". The LIN transceiver can be programmed to operate with lower slew in the normal mode. Refer to Table 14 for a detailed description on transition for each mode.
7.2.1
Normal Mode
This is the mode after the power-up. In normal mode, LDO, LIN Transceiver, Window Watchdog, Resistive divider and the line drivers are all turned on. All the blocks are completely functional. LDO is now capable of delivering maximum load current possible as per the device specifications. The LIN Transceiver is capable of sending the TX data from microcontroller to the LIN bus at a maximum rate of 20Kbps. Resistive divider is used to attenuate the battery voltage and relay drivers are used to drive the relay. EN signal is set to high and LIN, TX, RX pins can be driven into dominant (low) or recessive (high) states. If the junction temperature increases more than Totset, a warning flag is set in the diagnostic register, which can be read through the SPI interface.
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7.2.2
Standby Mode
Standby mode is a functional low-power mode where the LDO is switched into a low-power state with low drive capability and lower accuracy of the output voltage. LIN Transceiver is disabled. The LIN wake-up circuit and over-temperature monitor circuit is enabled. Window watchdog, TX timeout watchdog, Resistive divider, relay driver circuits are disabled. EN pin held low in this mode. TX pin is in recessive state (high). CS is pulled to VCC while SDI and SCLK outputs are pulled to VSS.
7.2.3
Sleep Mode
As a factory programming option on request the AS8520 offers as a replacement to the standby mode with sleep mode. Sleep mode is the most current saving mode. If EN is held low, the LDO, LIN Transceiver, the gate drivers, the resistive divider and the reset and window watchdog unit will be switched off. VCC is pulled down to zero. CS is low. The LIN wake-up circuit, oscillator and over-temperature monitor circuit is active. LIN bus is in recessive state (high). Only wake-up possible is through remote wake-up, through LIN pin, pulling it to dominant state for 100s typical (low), can change the state of the system.
7.2.4
Temporary Shutdown Mode
In this mode, the VCC is pulled down and the LDO is powered down. This mode is introduced to interface with other components which do not have a pin for the reset functionality. This provides an alternative way to reset those components interfacing with AS8520. This mode is default disabled but can be enabled by an OTP option. In this mode, all internal modules supplied by the LDO are disabled. Only the oscillator, control registers are enabled. The VCC output can be temporarily switched off and pulled to VSS. EN signal, RX, TX is pulled low and LIN Transceiver along with the LIN wake-up circuit is powered down. No remote wake-up functionality is possible. LIN bus enters into recessive state. The system goes out of this mode to normal mode after the time-out of an internal counter delay (Tshd). Normal mode to temporary shutdown transition will be controller by register bit in configuration register.
7.2.5
Thermal Shutdown State
If the junction temperature TJ is higher than Tsd, the AS8520 will be switched into the thermal shutdown mode. The transceiver is completely disabled. No wake-up functionality is available. Window watchdog, TX timeout watchdog and LDO are completely turned off. Only the overtemperature monitor would be working. As soon as the temperature returns back to Tret, the system enters normal mode. For more information on transition, see Table 14. Table 14. Transition Table Transition From mode To mode Stand-By Sleep Normal Mode
1
Interface LIN X-RS X-RS X-RS RX X-H X-H X-H
2
Reg. 0x05 D0 EN H-L H-L H
3 3
Flags rwake Uvbat X X X OT inactive inactive inactive Uvcc inactive set set Comments TX is high for TSTNDY_triggerr TX is high for 1 TSTNDY_triggerr The Control Bit is set through the 4-Wire SPI interface Temperature monitor output asserted (covered by scan)
TX H H
3
L L H
X X X
2
3
3
Temporary Shutdown OverTemperature Normal (LW) Normal (RW)
2
X
X-RS X X
X-H H-X H-X
2
2
X X H
X L-H X
3
L L L
3
X X set
X X X
set inactive inactive
set inactive inactive
2
2
Remote Wake up Event occurred on LIN The Control Bit is set through the 4-Wire SPI interface Temperature monitor output asserted (covered by scan)
Stand-By Mode
Temporary Shutdown OverTemperature
RS
H
H
L
H
X
X
inactive
set
RS
H
2
H
L
L
X
X
set
set
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Table 14. Transition Table Transition From mode Temporary Shutdown Mode OverTemperature Mode To mode Normal LIN RS-X Interface RX H-X
2
Reg. 0x05 D0 EN X L rwake X Uvbat X
Flags OT inactive Uvcc clear Comments Internal 128ms timer expired Temperature monitor output de-asserted (covered by scan) Remote Wake up Event occurred on LIN Temperature monitor output asserted (covered by scan)
TX X
Normal
RS-X
H-X
2
X
X
L
X
X
clear
clear
Normal Sleep Mode
3
RS-X
H-X
2
2
X
X
L
set
X
inactive
clear
OverTemperature All States Power Off
RS X
H
X X
X X
L X
X X
X L-H
3
set X
hold X
X
1. Chosen by factory programming option 2. Effect of Transition 3. Cause for Transition Note: L = low state, H = high state, OT = Over-temperature Reset, Uvcc = Undervoltage VCC, Uvbat = Undervoltage VBAT, rwake =remote wake, X = don't care.
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7.3 State Diagram
The complete functional state machine for AS8520 is illustrated in Figure 6. Some soft-states in the FSM like "TXWD Wait", "Standby Wait" and other "wait" states have been included for the sake of completeness. Figure 6. Finite State Machine Model for the AS8520 System
INIT0
por_vsup ! temp160
OVTEMP
OTP LOAD
otp_load
temp160 128msec temp160
Temp Shut
T s hu e m p t do wn
RESET TIMEOUT
reset timeout ! por_vcc || wwdtimeout test_en Standby & sleep
by RX
temp160
rwake
SLEEP
NORMAL
RX=0
o tp =0
WAIT_TEST
temp160
st
by an d
! st
and
_e n
mp n Te tdow u sh
Txwd_timeout
temp160
STANDBY
Temp own shutd
! por_vcc
p Tem own td s hu
TX=1
rw ak e_ wa it
WAIT_OTP
rwake
temp160
STANDBY WAIT
! por_vcc
! por_vcc || wwdtimeout
TXWD WAIT
temp160
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8 Application Information
8.1 Initialization
When the power supply is switched on, if VSUP > VSUVR_OFF, RESET_VSUP_N becomes inactive (high). After this, the voltage regulator starts with a default LDO output setting of 3.3V and Vuvr_off setting of 2.75V. If VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time TLoad. LOAD_OTP_IN_PREREG signal loads contents of OTP latch onto the pre-regulator domain register. This register gives actual settings of LDO, Vuvr_off and Reset Timeout period TRes. This is done because the OTP block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is deasserted after Reset Timeout period TRes (phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very slow ramp rates on VSUP (of the order of 0.5V/min). Figure 7. Initialization Sequence for AS8520
VSUP_POR_Threshold = 3.1V
VSUP
RESET_VSUP_N PHASE 1 Device Settings
LDO Off LDO On VCC Por Threshold = 2.75V LDO setting = 3.3V Reset Timeout = 4msec
PHASE 2
LDO On VCC Por Threshold = from OTP Block LDO setting = from OTP Block Reset Timeout = from OTP Block
VCC_POR_Threshold = 2.75V
VCC
RESET_VCC_N PORN_2_OTP
6 Cycles of RC-Oscillator
LOAD_OTP_IN_P REREG
RESET
If Phase 1 POR threshold != Phase 2 POR threshold Tres = Reset Timeout from OTP Block If Phase 1 POR threshold == Phase 2 POR threshold Tres = Reset Timeout from OTP Block
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Table 16. VSUP8.2 Wake-Up
If the regulator is put into sleep/standby mode, it can be woken up with the BUS interface. A transition on the BUS (high to low) with a minimum predefined low time (twake) puts the regulator into normal mode.
8.3 Over-Temperature Shutdown
If the junction temperature increases beyond Tsd the over-temperature recognition will be activated and the regulator voltage will be switched off. The VCC voltage drops down, the reset state is entered and the bus transceiver is switched off (recessive state). After TJ falls below Tret, the AS8520 will be initialized again. This initialization starts independently from the voltage levels on EN and BUS. Within the thermal shutdown mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. The operation of the AS8520 is possible between TJ (125C) and the switch off temperature Tsd, but small parameter differences can appear. After over-temperature switch-off, the IC initializes as explained in Initialization on page 20. The low slew mode for LIN Transceiver has to be selected again on re-initialization, if necessary.
8.4 LIN BUS Transceiver
The AS8520 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a de-bouncing unit.
8.4.1
Transmit Mode
During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit. Transmitting will be interrupted in the following cases: Sleep mode Thermal Shutdown active Master Reset (VSUP < Vsuvr_on) The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the AS8520 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k resistor in series with a diode to VBAT.
8.4.2
Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed.
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Figure 8. Receive Mode Impulse Diagram
V thr_max
60%
BUS
50% 40%
V thr_hys V thr_min
V thr_cnt
t < tdeb_BUS
t < tdeb_BUS
RX
8.5 RX and TX Interface
8.5.1 Input TX
The 5V input TX controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on TX leads to the LIN bus being pulled low (dominant state) too. The TX pin has an internal active pull up connected to VCC. This guarantees that an open TX pin generates a recessive BUS level. Figure 9. TX Input Circuitry
MCU VCC
VCC
AS8520
IPU_TXD
RC-Filter (10ns) TX
8.5.2
Output RX
The received BUS signal will be output to the RX pin: BUS < Vthr_cnt - 0.5 * Vthr_hys RX = low BUS > Vthr_cnt + 0.5 * Vthr_hys RX = high This output is a push-pull driver between VCC and GND with an output current of 1mA.
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Figure 10. RX Output Circuitry
AS8520
VCC
RX
MCU
8.6 MODE Input EN
The AS8520 is switched from normal mode to the standby/sleep mode with a falling edge on EN and keeping TX high for TSTNDY_trigger time. Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for AS8520 with a falling edge at EN can be done independently from the state of the bus transceiver. Device enters into Serial port mode (for factory test purpose only) by forcing EN low and driving TX high to low within Ttx_SP_trigger time after EN forced to low. This ensures the direct control of device to enter into Standby/Sleep mode by microcontroller using EN pin. Figure 11. EN Pin Functionality
Entry into Serial Port Mode
Ten_ENSCLK
EN
TX
RD WR
LEN1 LEN0
A4
D3
D2
D1
D0
Ttx_su
Normal Mode
TSTNDY_trigger Ttx_hd
Standby/Sleep Mode
Ttx_su Ttx_SP_trigger
Normal Mode Serial Port Mode Normal Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
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Figure 12. Enable Controlled via. MCU
Cload + MCU
EN VBAT VSUP LIN VSS VBAT_DIV VBAT LDRIVE1 LDRIVE2 AS8520
VCC RESET TX RX CS SDO SCLK SDI
+ 5V
If the application doesn't need the wake up capability of the AS8520, a direct connection EN to VCC is possible. In this case the AS8520 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via. VSUP signal as shown below. Figure 13. Permanent Normal Mode
Cload +
MCU
EN VBAT VSUP LIN VSS VBAT_DIV VBAT LDRIVE1 LDRIVE2
VCC RESET TX
+ 5V
AS8520
RX CS SDO SCLK SDI
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8.7 Serial Port Interface
The 4-wire interface is essentially used to control the relay driver, to shutdown LDO temporarily and to trigger the window watchdog. It is also used to access test mode and read out diagnostic information for the AS8520. The description of this interface and the protocol is explained below. Information on block status and errors can be displayed by diagnosis registers.
8.7.1
Device Configuration using 4-Wire Serial Port
The SPI interface can be used as interface between the AS8520 and an external microcontroller to configure the device and access the status information. The interface is a slave and then only the microcontroller can start the communication. The SPI protocol is very simple and the length of each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bit, 5 address/ configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done on each start of the SPI transaction. During the transaction, the SPI clock polarity will be fixed to the settings done. On the CS falling edge, the values on SCLK signal decide setting of the active SPI clock edge for data transfer. (see table below) Table 17. CS and SCLK CS FALL FALL ANY SCLK LOW HIGH ANY Description Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock. Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock. Serial data transfer edge is unchanged.
8.7.1.1
SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits. (see table below) Table 18. Command Bits Command Bits C0 C0 0 1 Reserved Command WRITE READ Reserved ADDRESS ADDRESS A4 Register Address or Transmission Configuration A3 A2 Description Writes data byte on the given starting address. Read data byte from the given starting address. A1 A0
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling), the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
8.7.1.2
Write Command
For Write command C0 = 0. After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next SPI clock edge samples it. These edges are selected as per Table 17. The following figures illustrate two examples of write command (without and with address self-increment.)
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Figure 14. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
0
RES1
RES0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Transfer edge
Sampling edge
Data D7 - D0 is moved to Address A4..A0 here
Figure 15. Protocol for Serial Data Write with Length = 4
CS
SCLK
SDI
RR A A A A A DD D D DD DD DD D DDD D D DD D DD D D DDD D DD D D D DD D DD D D D ES 0 ES 4 3 2 1 0 76 5 432 1076 5 432 1 0 76 5 432 1 076 5 432 10 76 5 432 10 10
SDO
Data D7-D0 is moved to Address A4-A0 here
Data D7-D0 is moved to Address A4-A0 +1 here
Data D7-D0 is moved to Address A4-A0 +2 here
Data D7-D0 is moved to Address A4-A0 +3 here
Data D7-D0 is moved to Address A4-A0 +4 here
8.7.1.3
Read Command
For Read command C0 = 1. After the command code C0 and two reserved bits, the address of register to be read has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. To transfer more bytes from consecutive addresses, SPI master has to keep active the SPI CS signal and the SPI clock as long as it desires to read data from the slave. Each bit of the command and address sections of the frame have to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next SPI clock edge samples it. Each bit of the data section of the frame has to be driven by the SPI slave on the SPI clock transfer edge and the SPI master on the next SPI clock edge samples it. These edges are selected as per Table 17. The following figures illustrate two examples of read command (without and with address self-increment.)
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Figure 16. Protocol for Serial Data Read with Length = 1
CS
SCLK
SDI
1
RES1
RES0
A4
A3
A2
A1
A0
SDO
D7
D6
D5
D4
D3
D2
D1
D0
Transfer edge
Sampling edge
Data D7 - D0 at Address A4..A0 is read here
Transfer edge
Sampling edge
Figure 17. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
1
RR EE AAAAA 43210 S1 S0
SDO
D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D DD D D D D 7 6 543 210 76 5 432 10 76 5432 10 76 5 43 21 0 76 543 21 0
Data D7-D0 at Address A4-A0 is read here
Data D7-D0 at Address A4-A0 +1 is read here
Data D7-D0 at Address A4-A0 +2 is read here
Data D7-D0 at Address A4-A0 +3 is read here
Data D7-D0 at Address A4-A0 +4 is read here
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8.7.1.4
Timing
The following figures illustrate timing waveforms and parameters. Figure 18. Timing for Writing
CS ... t CPS SCLK t CPHD t SCLKH t SCLKL ... t DIS t DIH t CSH
CLK polarity
SDI
DATAI
DATAI
...
DATAI
SDO
...
Figure 19. Timing for Reading
CS t SCLKH t SCLKL
SCLK
SDI
DATAI
DATAI t DOD t DOHZ
SDO
DATAO (D7 N )
DATAO (D0 0 )
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8.8 Control and Diagnosis Registers
The serial interface can be used as interface between the ASSP AS8520 and an external micro-controller. The interface is a slave and only the micro-controller can start the communication. This interface will be used for device configuration, entering into test mode and carrying out diagnostic options. Refer to Table 19 for details on the configuration registers.
8.8.1
Definition of Control and Status Registers
A total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 4-wire serial interface. Table 19 provides a description of all control and status registers. Table 19. Configuration Registers Addr Register Name POR Value Bit Type Description
Control and Configuration Register b[7:1] On OTP Interface POR_VCC 0 x 02 Control Register 0000_0000 0 1 b[7:4] b[3] Device Configuration Register On POR_VCC 0000_1011 b[2] b[1] b[0] b[7:1] 0 x 04 Device Control Register On POR_VSUP 0000_0001 b[0] b[7:1] 0 x 05 Temporary Shutdown Register On POR_VCC 0000_0000 b[0] b[7:1] On POR_VCC 0000_0000 b[0] b[7:2] b[1] b[0] R/W W R/W 0 1 Window Watch Dog Trigger Register Low Side Driver Data Register R/W 0 1 0 1 0 R/W 1 0 1 0 1 Reserved OTP feature is only for factory use! b[0] R/W OTP interface is disabled. OTP interface is enabled. When this bit is set, EN, TX, RX are used as OTP interface pads. These pads can be used for OTP programming. OTP interface is disabled on seeing high to low transition on RX (MODE). Reserved LIN Transceiver disabled LIN Transceiver enabled Over-Temperature Monitor disabled Over-Temperature Monitor enabled Low side Driver2 disabled Low side Driver2 enabled Low side Driver1 disabled Low side Driver1 enabled Reserved Slew control Low Slew Mode High Slew mode Reserved Temporary shutdown control bit No Temporary shutdown Enter into Temporary shutdown Reserved Window Watch Dog Trigger. This bit will be set by MCU to indicate trigger event. If this trigger occurs outside the Window of Watchdog counter, then RESET signal is asserted. Also on this trigger WWD counter is restarted and this bit will be cleared internally within 2 cycles of 128KHz clock. Reserved This bit is Data input to Low Side Driver 2 gate input This bit is Data input to Low Side Driver 1 gate input
0 x 03
0 x 06
0 x 07
On POR_VCC 0000_0000
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Table 19. Configuration Registers Addr Register Name POR Value Bit Type Description
Diagnosis Register b[7:0] are 8 LSB bits of the 24 bit Diagnostic Register b[7] b[6] 0 x 08 Diagnostic Register 1 On POR_VSUP 0000_001 b[5] b[4] b[3] b[2] b[1] b[0] b[7:2] b[1] b[0] 0 x 0A 0 x 0B 0 x 0C 0 x 0D 0 x 0E 0 x 0F 0 x 10 Backup Register 1 Backup Register 2 Backup Register 3 Backup Register 4 Backup Register 5 Backup Register 6 On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 b[7:0] R/W R R WWDT Window watchdog timeout (set on failure of Window watchdog timeout, cleared after C read RWAKE Remote Wakeup (set on Remote Wakeup event on LIN Bus, cleared after C read) Reserved OVVBAT Overvoltage VBAT (set when VSUP > Vovthh, cleared after C read) OTEMP140 Over-temperature warning (set when temp > Totset, cleared after C read) OTEMP160 Over-temperature Reset (set when temp > Tsd, cleared after C read) UVVCC Undervoltage VCC (set when VCC < Vuvr_on, cleared after C read) PORVSUP (set when VSUP < Vsuvr_on, cleared after C read) b[7:0] = DR[15:8] Next 8 LSB bits of the 24 bit Diagnostic Register. 0 x 09 Diagnostic Register 2 On POR_VSUP 0000_0000 Reserved TEMPSHUT this bit is set on entering into temporary shutdown state and cleared after C read. TXTIMEOUT Tx timeout of 1sec (set on TX low > 1sec, cleared after C read) Reserved Reserved Reserved Reserved Reserved Reserved This can be used to store configuration/status data during Sleep mode.
0 x 11
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
0 x 12
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
0 x 13
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
0 x 14
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
0 x 15
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
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Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
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Table 19. Configuration Registers Addr 0 x 16 Register Name Backup Register 7 Backup Register 8 POR Value On POR_VSUP 0000_0000 On POR_VSUP 0000_0000 Bit b[7:0] Type R/W Description This can be used to store configuration/status data during Sleep mode.
0 x 17
b[7:0]
R/W
This can be used to store configuration/status data during Sleep mode.
8.9 ESD/EMC REMARKS
8.9.1 General Remarks
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
8.9.2
ESD-Test
The AS8520 is tested according CDF-AEC-Q100-002 / MIL883-3015.7 (human body model), IEC 61000-4-2, JESD22-C101/ AEC-Q100-011, JESD22-A115/AEC-Q100-003.
8.9.3
EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for data and signal pins.
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Preliminary Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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9 Package Drawings and Markings
The device is available in a 24-pin QFN (6x6) package. Figure 20. Package Drawings
AYWWIZZ AS8520 51111Y
19 24
18
1
13
6
12
7
Table 20. Package Dimensions Symbol D E D1 E1 L b e A A1 0.80 4.40 4.4 0.35 0.25 mm Min Typ 6 6 4.50 4.50 0.40 0.30 0.65 0.85 0.203 0.9 4.60 4.60 0.45 0.35 Max
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Preliminary Data Sheet - R e v i s i o n H i s t o r y
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Revision History
Table 21. Revision History Revision Date Owner Description
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Preliminary Data Sheet - O r d e r i n g I n f o r m a t i o n
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10 Ordering Information
The devices are available as the standard products shown in Table 22. Table 22. Ordering Information Ordering Code AS8520-AQFT Description VCC = 5V Delivery Form Tape & Reel Package 24-pin QFN (6x6)
Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor
Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
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